1. Field of the Invention
The present invention relates to comparators and particularly to multiple input dynamic comparators.
2. State of the Art
In the field of circuit design, comparators function to compare the voltage level of two digital signals and to output a signal indicating whether they are equal or not. A multiple input comparator is designed to perform a parallel bit-by-bit comparison of two multiple bit digital bus signals and to indicate whether the two buses are the same or different. In this case, bit lines from each bus are paired and compared and if any of the bits of the two buses are different, the comparator outputs a signal that indicates that the two bus signals are not the same.
A dynamic comparator is a clocked comparator that pre-charges its output to a known state in a first pre-charge clock phase and performs the comparison in a second evaluate clock phase. FIG. 1 shows a prior art dynamic comparator which compares bit line signals a.sub.1 -a.sub.n of a bus A to bit line signals b.sub.1 -b.sub.n of a bus B. As shown, the comparator includes two devices P1 and N1 having opposite polarity and controlled by a clock signal CLK such that during a pre-charge phase (e.g. CLK=LOW), P1 is on and node X is pre-charged to VCC and N1 is off. During the evaluate stage (e.g. CLK=HIGH), N1 is on and P1 is off such that node X is pulled low or remains at its pre-charge voltage level depending on the comparison of the bit lines. For each pair of bit lines, the dynamic comparator includes a comparison sub-circuit coupled between devices N1 and P1 which, during the evaluate stage, either pulls node X towards ground when the bits are different or which maintains the pre-charge voltage at node X when the bits are the same.
Referring to FIG. 1, each comparison sub-circuit compares two bit line pairs (e.g. a.sub.1 and b.sub.1). Each sub-circuit has two parallel branches B1 and B2--each branch including two series coupled devices. Ideally, in operation, if a.sub.n .noteq.b.sub.n then both of the devices in one of the branches will be on while both of the devices in the other of the branches will be off. As a result, a path between node X and ground is created such that when device N1 is on during the evaluate stage, node X is pulled to ground.
For instance, if a.sub.1 =HIGH and b.sub.1 =LOW, then N2 and N3 will both be on while devices N4 and N5 are both off, thereby forming a path from node X to ground during the evaluate stage through devices N2 and N3. On the other hand if a.sub.1 =b.sub.1, then at least one device is off in each branch and no path is created between node X and ground during the evaluate stage such that node X remains at its pre-charge state. For instance if a.sub.1 =b.sub.1 =HIGH then device N2 is on and device N3 is off while device N4 is off and device N5 is on.
The problem that occurs in this type of circuit is that during the pre-charge phase, node X begins to charge to VCC and, at the same time, the A and B bus input signals are also being set-up. As a result, during the pre-charge phase some of the devices that are directly connected to node X will be switched "on" as node X is being pre-charged. For instance, if a.sub.1 =b.sub.1 =HIGH is applied to the gates of devices N2-N4 while node X is pre-charging, device N2, which is connected directly to node X, will turn on during the pre-charge phase. As a result, the parasitic capacitance C.sub.1 associated with node n.sub.1 combines with the parasitic capacitance C.sub.x associated with node X causing an initial drop in voltage at node X during pre-charge. After this initial drop, however, since N1 is off and P1 is on, P1 continues to pre-charge node X to VCC. Unfortunately, the effect of the initial drop is that it takes longer to pre-charge node X. In addition, in the case in which more than one pair of bits matches, more of the parasitic capacitances C.sub.2, C.sub.3, . . . C.sub.n combine and cause a proportional drop in voltage on node X during pre-charge.
The present invention describes a dynamic comparator having improved pre-charge and set-up times that avoids the effects of unwanted parasitic capacitances.